Activity 3.3.4 — Unit 3 Review & Assessment

Learning Objectives

By the end of this lesson, students will be able to:

Demonstrate understanding of sequential logic concepts
Analyze and design flip-flop circuits
Design and analyze both asynchronous and synchronous counters
Apply knowledge to create complete digital systems
Identify appropriate ICs for specific applications

Vocabulary (Unit 3 Review)

Term	Definition
Flip-Flop	A bistable memory element that stores one bit; changes state on clock edges
D Flip-Flop	Data flip-flop; captures input D on clock edge, transfers to Q
JK Flip-Flop	Versatile flip-flop with J (set) and K (reset) inputs; J=K=1 toggles
Edge-Triggered	Responds only on the rising (↑) or falling (↓) edge of the clock
Level-Triggered	Responds continuously while clock is HIGH or LOW (latch behavior)
Propagation Delay	Time between input change and corresponding output change
Asynchronous	Ripple operation; each stage’s output clocks the next stage
Synchronous	All flip-flops share the same clock; change simultaneously
Counter	Sequential circuit that counts through a sequence of states
Modulus (Mod-N)	The number of unique states a counter cycles through
Presettable	A counter that can be loaded with a specific starting value
Shift Register	Sequential circuit that shifts data bits left or right on each clock
Timing Diagram	Graph showing signal levels (HIGH/LOW) over time

Part 1: Key Concepts Review

Flip-Flops

Flip-Flop	Symbol	Behavior
D Flip-Flop	Data input D, Clock CLK	Q = D on clock edge (store/transfer)
JK Flip-Flop	Inputs J, K, Clock CLK	J=K=0: hold; J=0,K=1: reset; J=1,K=0: set; J=K=1: toggle
SR Flip-Flop	Set and Reset inputs	Set=1: Q=1; Reset=1: Q=0

Key Terms

Term	Definition
Edge-Triggered	Circuit responds only on rising or falling clock edge
State	The current output value(s) of a sequential circuit
Timing Diagram	Graph showing how signals change over time
Propagation Delay	Time delay between input change and output change
Modulus	Number of unique states in a counter

Part 2: Flip-Flop Review Problems

Problem 1: D Flip-Flop Analysis

Given the D flip-flop circuit below, determine the output waveform for Q:

D ──────▶[D   Q]─── Q
         [    ]
CLK ─────[CLK   ]

Initial: Q = 0
Clock:   ┌───┐   ┌───┐   ┌───┐   ┌───┐
         │   │   │   │   │   │   │   │
         └───┘   └───┘   └───┘   └───┘
         
D:       ┌───┐       ┌───┐
         │   │       │   │
         └───┘       └───┘

Show Solution

Q:       ┌───┐   ┌───┐   ┌───┐   ┌───┐
         │   │   │   │   │   │   │   │
         └───┘   └───┘   └───┘   └───┘

D is sampled on rising edge:
- Edge 1: D=1 → Q becomes 1
- Edge 2: D=0 → Q becomes 0
- Edge 3: D=1 → Q becomes 1
- Edge 4: D=0 → Q becomes 0

Q follows D with one clock cycle delay.

Problem 2: JK Flip-Flop Toggle Mode

What is the output Q when J = K = 1 (toggle mode)?

Show Solution

When J = K = 1, the flip-flop toggles on each clock edge:

Q changes from 0 to 1, or from 1 to 0
This is how counters toggle on each clock pulse

Part 3: Shift Register Review

Types of Shift Registers

Type	Full Name	Function
SISO	Serial In, Serial Out	Data enters one bit at a time, exits one bit at a time
SIPO	Serial In, Parallel Out	Data enters serially, all bits available in parallel
PISO	Parallel In, Serial Out	All bits loaded in parallel, exit serially
PIPO	Parallel In, Parallel Out	Parallel load and parallel output

Practice: SIPO Shift Register Analysis

A 4-bit SIPO register has 1011 loaded in parallel. What is the output after 3 clock pulses if data input (serial in) = 0?

Show Solution

Initial: Q3 Q2 Q1 Q0 = 1011

Clock 1: Shift right, serial in = 0 Q3 Q2 Q1 Q0 = 0101

Clock 2: Shift right, serial in = 0
Q3 Q2 Q1 Q0 = 0010

Clock 3: Shift right, serial in = 0 Q3 Q2 Q1 Q0 = 0001

After 3 clocks: 0001 (original LSB has shifted out)

Part 4: Counter Review

Asynchronous vs Synchronous Counters

Feature	Asynchronous (Ripple)	Synchronous
Clock	Only first FF gets clock	All FFs share clock
Delay	Accumulates through chain	Simultaneous change
Speed	Slower at high frequencies	Faster, higher max freq
Complexity	Simple	More complex logic
Example ICs	74LS90, 74LS93	74LS163, 74LS193

Counter IC Quick Reference

IC	Type	Modulus	Special Features
74LS90	Decade	10	BCD output, separate divide-by-2 and divide-by-5
74LS93	4-bit binary	16	Separate divide-by-2 and divide-by-8
74LS163	4-bit binary	16	Synchronous load, clear, count enable
74LS193	4-bit binary	16	Up/down counting, parallel load, clear

Part 5: Practice Problems

Problem 1: Timing Diagram Analysis

Draw the Q output for a JK flip-flop (toggle mode, J=K=1) given this clock signal. Initial Q = 0.

Clock:    ┌───┐   ┌───┐   ┌───┐   ┌───┐   ┌───┐
          │   │   │   │   │   │   │   │   │   │   │
          └───┘   └───┘   └───┘   └───┘   └───┘

Show Solution

Q:       ┌───┐   ┌───┐   ┌───┐   ┌───┐   ┌───┐
          │   │   │   │   │   │   │   │   │   │   │
          └───┘   └───┘   └───┘   └───┘   └───┘
          ↑       ↑       ↑       ↑       ↑
         TOGGLE  TOGGLE  TOGGLE  TOGGLE  TOGGLE

Q toggles on each rising edge:
- Initial: 0
- Edge 1: 1
- Edge 2: 0
- Edge 3: 1
- Edge 4: 0

Problem 2: Modulus Counter Design

How would you modify a 74LS163 to create a modulus-12 counter (counts 0-11)?

Show Solution

Method: Use synchronous clear

Count normally from 0 to 11 (binary 0000 to 1011)
When output reaches 1100 (12), clear on next clock

Implementation:

Detect when Q3=1, Q2=0, Q1=0, Q0=0 (count = 12)
Connect to CLR input (or use load with all zeros)

Logic: CLR = Q3 AND NOT Q2 AND NOT Q1 AND NOT Q0

When count = 12, CLR goes HIGH, next clock clears to 0000.

Problem 3: Decade Counter Analysis

A 74LS90 is wired as a BCD decade counter (counts 0-9). What is the output frequency at QA if the input clock is 100 Hz?

Show Solution

The 74LS90 BCD counter divides by 10:

Input: 100 Hz
Output at QD: 100/10 = 10 Hz

Since QD is the MSB of the BCD count, it toggles once per 10 clock cycles, giving 10 Hz output.

Part 6: System Design Review

Now Serving Display

This project displays customer numbers using:

Two decade counters (74LS90 or 74LS163)
Two BCD-to-7-segment decoders (7447)
Two 7-segment displays
Increment button

60-Second Timer

This project requires:

Two 74LS193 counters (cascaded for ones and tens)
Two 7447 decoders
Two 7-segment displays
Start/Stop/Reset controls
Clock source (555 timer or function generator)
Zero detection logic

Part 7: Self-Assessment Checklist

Complete this checklist to verify your understanding:

Flip-Flops

I can explain the difference between level-triggered and edge-triggered
I can draw the truth table for D and JK flip-flops
I can analyze timing diagrams for flip-flop circuits

Shift Registers

I understand the four types of shift registers
I can trace data through a shift register
I can connect shift registers for specific applications

Counters

I can distinguish between asynchronous and synchronous counters
I can design a synchronous counter using JK flip-flops
I can use excitation tables for counter design
I understand propagation delay and its effects

Integrated Circuits

I can use the 74LS90 decade counter
I can use the 74LS93 binary counter
I can use the 74LS163 synchronous counter
I can use the 74LS193 up/down counter with parallel load

System Design

I can design a Now Serving display system
I can design a 60-second timer with controls
I can cascade counters for multi-digit displays

Summary

Unit 3 covered sequential logic design including:

Flip-flops as the basic storage elements (D, JK, SR)
Shift registers for serial-to-parallel and parallel-to-serial conversion
Asynchronous counters using ripple clocking (simple but slow)
Synchronous counters using common clock (faster but more complex)
Counter ICs (74LS90, 74LS93, 74LS163, 74LS193)
Complete systems including Now Serving displays and timers

Key Reminders

Edge-triggered flip-flops sample inputs on clock transitions
JK flip-flops toggle when J=K=1
Synchronous counters change all outputs simultaneously
Use parallel load to create custom modulus counters
Cascade counters using carry/borrow outputs for extended range

Custom activity — adapted from PLTW Digital Electronics