Activity 3.1.3 — Shift Registers
Learning Objectives
By the end of this lesson, students will be able to:
- Define a register and explain its purpose in digital systems
- Describe how shift registers move data one bit per clock pulse
- Identify and compare the four types of shift registers (SISO, SIPO, PISO, PIPO)
- Interpret timing diagrams for shift register operation
- Apply shift registers in serial-to-parallel and parallel-to-serial conversions
Vocabulary
Vocabulary (click to expand)
| Term | Definition |
|---|---|
| Register | A group of flip-flops that store multiple bits of data |
| Shift Register | A register where data moves (shifts) one position per clock pulse |
| Serial Data | Data transferred one bit at a time sequentially |
| Parallel Data | Data transferred multiple bits simultaneously |
| Bit-Serial | One bit per time slot |
| Parallel-in-Serial-out (PISO) | Shift register that accepts parallel input and produces serial output |
| Serial-in-Parallel-out (SIPO) | Shift register that accepts serial input and produces parallel output |
Part 1: What is a Register?
A register is a group of flip-flops used to store multiple bits of data. While a single flip-flop stores 1 bit, an n-bit register stores n bits.
Example: 4-Bit Register
D3 ──▶ Q3 ──┐
D2 ──▶ Q2 ──┤
D1 ──▶ Q1 ──┼──▶ 4-bit parallel output
D0 ──▶ Q0 ──┘
┌─────┐
CLK ─┤ │
└─────┘All flip-flops share a common clock, so all bits are stored simultaneously.
Key insight: Registers are the building blocks of memory. A computer’s register file contains dozens of registers, each storing multiple bits.
Part 2: Shift Registers Explained
A shift register is a special type of register where data moves (shifts) one position per clock pulse.
How Shift Registers Work
Each flip-flop’s output connects to the next flip-flop’s input:
┌───┐ ┌───┐ ┌───┐ ┌───┐
Serial │D │ │D │ │D │ │D │
Input ──┤ ├───┤ ├───┤ ├───┤ ├─ Q3 (MSB)
└───┘ └───┘ └───┘ └───┘
│Q │Q │Q │Q
▼ ▼ ▼ ▼
FF0 FF1 FF2 FF3Operation:
- Data enters at FF0
- On each clock pulse, data shifts one position to the right
- After 4 clock pulses, data that was at input is now at Q3
Part 3: Types of Shift Registers
1. SISO — Serial In, Serial Out
Data enters one bit at a time and exits one bit at a time.
SI ──▶ FF0 ──▶ FF1 ──▶ FF2 ──▶ FF3 ──▶ SO
CLK │ CLK │ CLK │ CLK │
└────────┴────────┴────────┘Use case: Long delay lines, FIFO buffers
2. SIPO — Serial In, Parallel Out
Data enters serially but can be read out in parallel.
SI ──▶ FF0 ──▶ FF1 ──▶ FF2 ──▶ FF3
CLK │ CLK │ CLK │ CLK │
└────────┴────────┴────────┘
│ │ │ │
▼ ▼ ▼ ▼
Q0 Q1 Q2 Q3 (parallel outputs)Use case: Converting serial data to parallel (e.g., receiving data from a computer)
3. PISO — Parallel In, Serial Out
Parallel data loads in, then shifts out serially.
D0 ──▶│D │D │D │D◀── Q3 (from prev)
D1 ──▶│FF0 │FF1 │FF2 │FF3
D2 ──▶│ │ │ │ SO ──▶
D3 ──▶│ │ │ │ (serial out)
▼ │ │ │
├─────┘ │ │
│ │ │
│ LOAD/SHIFT ◀───┘
│ │
└────────────┘Use case: Sending parallel data over serial communication lines
4. PIPO — Parallel In, Parallel Out
Data loads in parallel and shifts out in parallel.
D0 ──▶│D │D │D │D◀──
D1 ──▶│FF0 │FF1 │FF2 │FF3
D2 ──▶│ │ │ │
D3 ──▶│ │ │ │
▼ ▼ ▼ ▼
Q0 Q1 Q2 Q3
(parallel output)Use case: Temporary storage, data transfer between parallel devices
Key insight: SIPO and PISO are the most common types. SIPO converts serial data (from wires) to parallel (for displays/processors). PISO converts parallel data to serial (for transmission).
Part 4: 4-Bit Shift Register with D Flip-Flops
Let’s build a 4-bit SIPO shift register using D flip-flops.
Circuit Diagram
┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐
D0 ──┤ D Q ├───┤ D Q ├───┤ D Q ├───┤ D Q ├── Q3
│ FF0 │ │ FF1 │ │ FF2 │ │ FF3 │
Q0'└─────────┘ │ │ │ │ │ │
│ │ │ │ │ │
SI ─────────────────┴─────────┴───┴─────────┴───┘
(serial in) │ │ │ │
└─────────┴─────────┴─────────┘
CLKWait - that’s not quite right. Let me redraw:
Serial Input (SI)
│
┌─────────┼─────────┐
│ │ │
│ ┌─────┴─────┐ │
│ │ D Q0 │ │
│ └──────────┘ │
│ │ │
│ │ Q0 │
│ ┌─────┴─────┐ │
│ │ D Q1 │ │
│ └──────────┘ │
│ │ │
│ │ Q1 │
│ ┌─────┴─────┐ │
│ │ D Q2 │ │
│ └──────────┘ │
│ │ │
│ │ Q2 │
│ ┌─────┴─────┐ │
│ │ D Q3 │ │
│ └──────────┘ │
│ │ │
└─────────┼────────┘
│
Q3
│
Parallel Output
CLK (common to all)Actually, a cleaner view:
SI ──┬──► D0 ──► Q0 ──┬──► D1 ──► Q1 ──┬──► D2 ──► Q2 ──┬──► D3 ──► Q3
│ │ │ │
│ ┌─────┐ │ ┌─────┐ │ ┌─────┐ │ ┌─────┐
└───┤ D │ └───┤ D │ └───┤ D │ └───┤ D │
│ FF0│ │ FF1│ │ FF2│ │ FF3│
│ │ │ │ │ │ │ │
CLK │ CLK │ CLK │ CLK │
└─────────────┴─────────────┴─────────────┘
Common CLKOperation
- Clock 1: SI (bit 0) loads into FF0. Q0 = bit 0
- Clock 2: Q0 shifts to FF1, new SI (bit 1) loads into FF0
- Clock 3: Bit 0 → FF2, Bit 1 → FF1, Bit 2 → FF0
- Clock 4: All bits now available at Q0-Q3
Part 5: Timing Diagram
Let’s trace what happens when we input the binary number 1011:
Clock: ─────┐ ┌────┐ ┌────┐ ┌────┐ ┌────┐
│ │ │ │ │ │ │
└────┘ └────┘ └────┘ └────┘
↑ ↑ ↑ ↑
clock1 clock2 clock3 clock4
Serial ─────┐ ┌────┐ ┌────┐
Input: │ │ │ │
(1011) ────┴────┴────┴────
bit0 bit1 bit2 bit3
(1) (0) (1) (1)
Q0: ───────────────┐ ┌────┐
│ │
└────┘
(becomes 1 at clock1)
Q1: ───────────────────────┐ ┌────┐
│ │
└────┘
(becomes 1 at clock2)
Q2: ───────────────────────────────┐
└────
(becomes 0 at clock3)
Q3: ───────────────────────────────────┐
└────
(becomes 1 at clock4)After 4 clock pulses:
- Q3 = 1 (original bit 0, the first bit entered)
- Q2 = 1 (original bit 1)
- Q1 = 0 (original bit 2)
- Q0 = 1 (original bit 3, the last bit entered)
Wait, that’s reversed! Let me fix:
Clock: ─────┐ ┌────┐ ┌────┐ ┌────┐
│ │ │ │ │ │
└────┘ └────┘ └────┘ └────┘
↑ ↑ ↑ ↑
clock1 clock2 clock3 clock4
SI: ────┐ ┌────┐ ┌────┐ ┌─────────
│ │ │ │ │
└───┘ └───┘ └───┘
bit0=1 bit1=0 bit2=1 bit3=1
Q0: ────┐───────────────────────────────────
│ (becomes bit0=1 at clock1)
└───────────────────────────────────
Q1: ──────────────────┐
│ (becomes bit0=1 at clock2)
└───────────────────────
Q2: ──────────────────────────┐
│ (becomes bit1=0 at clock3)
└──────────────────
Q3: ──────────────────────────────────┐
│ (becomes bit2=1 at clock4)
└─────────────After clock 4: Q3=Q2=Q1=Q0 = 1011 ✓
Part 6: The 74LS194 Universal Shift Register
The 74LS194 is a 4-bit bidirectional universal shift register.
Features
- Parallel load (all 4 bits at once)
- Shift left
- Shift right
- Hold (no change)
Pinout
┌─────────────────────┐
P0 ─┤ 1 16 ├─ VCC
P1 ─┤ 2 74LS194 15 ├─ Q3
P2 ─┤ 3 14 ├─ Q2
P3 ─┤ 4 13 ├─ Q1
SR ─┤ 5 12 ├─ Q0
SL ─┤ 6 11 ├─ S0 (mode select)
CLK ─┤ 7 10 ├─ S1 (mode select)
MR' ─┤ 8 9 ├─ P3 (parallel input)
└─────────────────────┘Mode Control
| S1 | S0 | Mode |
|---|---|---|
| 0 | 0 | Hold |
| 0 | 1 | Shift Right (toward Q3) |
| 1 | 0 | Shift Left (toward Q0) |
| 1 | 1 | Parallel Load |
Pin Descriptions
| Pin | Function |
|---|---|
| P0-P3 | Parallel inputs |
| Q0-Q3 | Parallel outputs |
| SR | Serial Right input |
| SL | Serial Left input |
| S0, S1 | Mode select pins |
| CLK | Clock input (rising edge) |
| MR’ | Master Reset (active LOW, async clear) |
Key insight: The 74LS194 is “bidirectional” - it can shift left or right. It’s also “universal” - it can operate as SISO, SIPO, PISO, or PIPO depending on mode selection.
Practice Problem — Identify the Register Type
For each scenario, identify which type of shift register is needed:
-
You receive 8 bits one at a time from a computer and want to display them all at once on 8 LEDs.
-
You have 8 switches and want to send their states out one bit at a time over a single wire.
-
You need to delay a signal by exactly 5 clock cycles.
Show Solution
1. SIPO (Serial In, Parallel Out)
- Serial input from computer
- Parallel output to LEDs
2. PISO (Parallel In, Serial Out)
- Parallel inputs from switches
- Serial output to single wire
3. SISO (Serial In, Serial Out)
- Input: 1 bit
- Output: same bit after 5 clock cycles
- Creates a delay linePractice Problem — Timing Diagram
A 74LS194 is initially cleared (Q=0000). Serial input data = 1010 is shifted in from the right (SR input). Draw the Q outputs after each clock.
Initial: Q3 Q2 Q1 Q0 = 0000
Clock 1: SR = 1 (bit 0 of 1010) Clock 2: SR = 0 (bit 1) Clock 3: SR = 1 (bit 2) Clock 4: SR = 0 (bit 3)
What are the Q outputs after each clock?
Show Solution
Initial: Q3 Q2 Q1 Q0 = 0000
Clock 1: Shift right
- New: Q3=Q2, Q2=Q1, Q1=Q0, Q0=SR(1)
Result: 0001
Clock 2: Shift right
- New: Q3=Q2(0), Q2=Q1(0), Q1=Q0(1), Q0=SR(0)
Result: 0010
Clock 3: Shift right
- New: Q3=Q2(0), Q2=Q1(1), Q1=Q0(0), Q0=SR(1)
Result: 0101
Clock 4: Shift right
- New: Q3=Q2(1), Q2=Q1(0), Q1=Q0(1), Q0=SR(0)
Result: 1010 ✓
Final result matches input: 1010Part 7: Applications of Shift Registers
1. Serial-to-Parallel Conversion
Computers send data serially (one bit at a time) over networks. A SIPO shift register collects this data and presents it in parallel form.
Computer ──(serial)──▶ SIPO ──▶ Parallel data for processing
│
┌──────┘
Collects 8 bits
Then outputs all at once2. Parallel-to-Serial Conversion
Microprocessors process data in parallel but may need to transmit serially.
Switches/ ──▶ PISO ──▶ Serial transmission ──▶ Another device
Sensors3. Data Storage and Delays
Shift registers can introduce precise time delays in digital systems.
4. Arithmetic Operations
Shift registers enable:
- Multiplication by 2 (left shift)
- Division by 2 (right shift)
5. LED Scrolling Displays
Scrolling LED matrices use shift registers to turn individual LEDs on/off as the display refreshes.
Summary
Key takeaways from this lesson:
- Registers store multiple bits using groups of flip-flops
- Shift registers move data one position per clock pulse
- Four types: SISO, SIPO, PISO, PIPO - each serves different purposes
- 74LS194 is a universal bidirectional shift register IC
- Applications: serial-parallel conversion, delays, arithmetic, displays
Key Reminders
- Data in a shift register moves one position per clock edge
- SIPO is used to receive serial data in parallel form
- PISO is used to transmit parallel data serially
- The 74LS194 can shift left, shift right, load parallel, or hold
- Shift registers are essential for communication between serial and parallel devices
Custom activity — adapted from PLTW Digital Electronics