Activity 2.1.2 — AOI Circuit Analysis

Learning Objectives

By the end of this lesson, students will be able to:

Analyze a given logic circuit diagram and determine its Boolean expression
Construct truth tables from circuit diagrams
Trace signal paths from inputs through multiple gates to the output
Identify intermediate expressions at each gate output
Distinguish between different gate configurations (AND-OR, OR-AND, NAND-NAND)
Apply the analysis process to circuits with 2, 3, and 4 inputs

Vocabulary

Vocabulary (click to expand)

Term	Definition
Circuit Analysis	The process of determining the truth table and Boolean expression from a given logic circuit diagram
Intermediate Expression	The Boolean expression at the output of a gate that is not a primary input or final output
Signal Path	The route that an electrical signal follows from an input through one or more gates to the output
Gate Propagation	The delay between an input change and the corresponding output change (important for timing, not covered in detail here)
Subexpression	A portion of a larger Boolean expression, typically representing the output of an intermediate gate
AOI Configuration	AND-OR-Invert circuit structure; AND gates feed into an OR gate

Part 1: The Analysis Process

When you are given a logic circuit and asked to find its truth table and Boolean expression, you perform circuit analysis. This is the reverse of what you will do in the next lesson (implementation), where you start with an expression and build a circuit.

Step-by-Step Analysis Process

flowchart LR
    A["1. Identify\nGate Types"] --> B["2. Trace\nSignal Paths"]
    B --> C["3. Write Intermediate\nExpressions"]
    C --> D["4. Combine for\nFinal Expression"]
    D --> E["5. Build\nTruth Table"]

Step 1: Identify all gate types and their connections

Count the inputs on each gate
Note which gates connect to which
Identify if any gates are inverted (have bubbles)

Step 2: Trace signal paths from inputs to output

Start at the leftmost inputs
Follow each signal through the gates
Identify where signals split (fan-out) or combine

Step 3: Write intermediate expressions

Label each gate output with its Boolean expression
Start with gates that have only primary inputs
Work toward gates that use other gate outputs

Step 4: Combine to get the final expression

Substitute intermediate expressions into later expressions
Simplify the final result if possible

Step 5: Build the truth table

List all input combinations in binary order
Evaluate the final expression for each combination

Key insight: Work from left to right, one gate at a time. Never try to evaluate the whole circuit at once — break it into pieces!

Part 2: Worked Examples

Worked Example 1 — Simple 2-Input AND-OR Circuit

Circuit Description:

flowchart LR
    A[A] --- AND1[AND]
    B[B] --- AND1
    AND1 -->|P = AB| OR1[OR]
    C[C] --- OR1
    D[D] --- OR1
    OR1 --> Z[Z]

This is actually an AND-OR circuit with 4 inputs: A and B go to the AND gate, C and D bypass the AND gate and connect directly to the OR gate.

Step 1-2: Identify gates and paths

AND gate: inputs A and B
OR gate: inputs from AND gate output and inputs C and D

Step 3: Write intermediate expressions

Output of AND gate: $P = AB$ (let’s call this intermediate node P)
Final output: $Z = P + C + D$

Step 4: Combine $$Z = AB + C + D$$

Step 5: Build truth table

A	B	C	D	$AB$	$Z = AB + C + D$
0	0	0	0	0	0
0	0	0	1	0	1
0	0	1	0	0	1
0	0	1	1	0	1
0	1	0	0	0	0
0	1	0	1	0	1
0	1	1	0	0	1
0	1	1	1	0	1
1	0	0	0	0	0
1	0	0	1	0	1
1	0	1	0	0	1
1	0	1	1	0	1
1	1	0	0	1	1
1	1	0	1	1	1
1	1	1	0	1	1
1	1	1	1	1	1

SOP Expression: From truth table rows where Z = 1 $$Z = AB + C + D$$

This expression is already in SOP form! Notice the truth table has 16 rows because there are 4 inputs.

Worked Example 2 — 3-Input Circuit with Multiple Gates

Circuit Description:

A ----+\    _____
      | +--|     \
B ----+  (OR)     \
          |        \
C --------+         )---+--- Z
          |        /   |
D --------+-------/    |
                        |
E ----------------------+

Step 1-2: Identify gates and connections

OR gate: inputs A, B (and C, D)
AND gate: inputs from OR output and E

Step 3: Write intermediate expressions

OR output: $P = A + B + C + D$
Final output: $Z = P \cdot E = (A + B + C + D)E$

Step 4: Combine $$Z = E(A + B + C + D)$$

Step 5: Build truth table (5 inputs = 32 rows — showing key rows)

A	B	C	D	E	$P = A+B+C+D$	$Z = P \cdot E$
0	0	0	0	0	0	0
0	0	0	0	1	0	0
0	0	0	1	0	1	0
0	0	0	1	1	1	1
0	1	0	0	1	1	1
1	1	1	1	0	1	0
1	1	1	1	1	1	1

SOP Expression: Expand $E(A + B + C + D)$ $$Z = EA + EB + EC + ED$$

Key insight: The distributive property allows us to expand $E(A + B + C + D)$ into $EA + EB + EC + ED$. This is the SOP form that can be implemented with AND-OR logic.

Worked Example 3 — Circuit with Inverters

Circuit Description:

flowchart LR
    A[A] --> NOT1[NOT]
    NOT1 -->|\overline{A}| AND1[AND]
    B[B] --- AND1
    C[C] --- AND1
    D[D] --- AND1
    AND1 --> Z[Z]

Note: The symbol (|) indicates an inverter on input A.

Step 1-2: Identify gates

Inverter on input A
AND gate: inputs are $\overline{A}$, B, C, and D

Step 3: Write expressions $$Z = \overline{A} \cdot B \cdot C \cdot D = \overline{A}BCD$$

Step 4-5: Truth table and SOP

The truth table has 16 rows (4 inputs). The output Z = 1 only when:

A = 0 (so $\overline{A}$ = 1), AND
B = 1, AND
C = 1, AND
D = 1

SOP Expression: $Z = \overline{A}BCD$

Truth Table (key rows only):

A	B	C	D	Z
0	1	1	1	1
All other combinations				0

Only 1 row out of 16 has Z = 1. This makes sense: the minterm $\overline{A}BCD$ is true for exactly one combination.

Part 3: Common Gate Configurations

AND-OR Configuration (SOP Implementation)

flowchart LR
    A[A] --- AND1[AND]
    B[B] --- AND1
    AND1 --> OR1[OR]
    C[C] --- OR1
    D[D] --- OR1
    OR1 --> Z["Z = AB + C + D"]

Expression: $Z = AB + C + D$

This is the natural form for AOI logic implementation.

OR-AND Configuration (POS Implementation)

flowchart LR
    A[A] --- OR1[OR]
    B[B] --- OR1
    OR1 --> AND1[AND]
    C[C] --- OR2[OR]
    D[D] --- OR2
    OR2 --> AND1
    AND1 --> Z["Z = (A+B)(C+D)"]

Expression: $Z = (A + B)(C + D)$

Note: This is not the same as A + B + C + D. Parentheses matter in Boolean algebra!

NAND-NAND Configuration (Universal Gate Implementation)

A --+\    _____
    | +--|     \
B --+  (NAND)   \
               )---+--- Z (through two NAND stages)
C --+\    _____/   |
    | +--|     \   |
D --+  (NAND)   +--|____/

NAND-NAND logic is equivalent to AND-OR logic (this is a preview of DeMorgan’s theorems). It is important because NAND gates are often cheaper and faster than separate AND/OR gates.

Part 4: Analysis Tips and Tricks

Tip 1: Label Intermediate Points

When analyzing complex circuits, label intermediate gate outputs with letters (P, Q, R, etc.):

A ---+\    _____
     | +--|     \
B ---+  (OR)     \    _____
             +----+--|     \
C ------------/    |  | AND   )--- Z
                    +--|_____/
D -----------------/

Let P = output of OR gate = A + B + C
Final: Z = P · D = (A + B + C)D

Tip 2: Handle Bubbles Carefully

A bubble (inversion) on a gate input or output affects the expression:

Inverter on input: changes 0 to 1 and 1 to 0 in the minterm
Bubble on gate input: the signal is inverted before entering the gate

Example: If input A goes into an inverter, and the inverter output goes to a gate, use $\overline{A}$ at that gate.

Tip 3: Verify Your Work

Always check your derived expression against the original circuit:

Does every input go somewhere?
Are all gate connections accounted for?
Do bubbles correspond to inversions in the expression?

Practice Problem — Basic Circuit Analysis

Problem 1: Analyze the following circuit and write the Boolean expression.

A -----+
       |   _____
B -----+--|     \
       |  | AND   )-----------+
       +--|_____/             |
                               |   _____
C -----------------------------+--|     \
                               |  | OR    )--- Z
D -----------------------------+--|_____/
                               |
E -----------------------------+

Show Solution

Step 1: Identify gates

AND gate: inputs A, B, and C
OR gate: inputs from AND gate, D, and E

Step 2: Write expressions

AND output: $P = ABC$
OR output: $Z = P + D + E$

Step 3: Final expression $$Z = ABC + D + E$$

Truth Table (partial — showing where Z = 1):

A	B	C	D	E	$ABC$	$Z$
0	0	0	0	0	0	0
0	0	0	0	1	0	1
0	0	0	1	0	0	1
…	(D or E = 1)				0	1
1	1	1	0	0	1	1
1	1	1	0	1	1	1
1	1	1	1	0	1	1
1	1	1	1	1	1	1

Z = 1 for all rows where D = 1, E = 1, or ABC = 1.

Practice Problem — Circuit with Inversion

Problem 2: Analyze the following circuit and write the Boolean expression.

A -----+
       (|)
       |  _____
B -----+--|     \
       | | AND   )----------- Z
C -----+--|_____/
       |
D -----+

Show Solution

Analysis:

Input A goes through an inverter (bubble), becoming $\overline{A}$
Inputs B, C, D go directly to the AND gate

Expression: $$Z = \overline{A} \cdot B \cdot C \cdot D = \overline{A}BCD$$

Truth Table: Z = 1 only when A=0, B=1, C=1, D=1 (one row out of 16)

SOP: $Z = \overline{A}BCD$

Practice Problem — Multi-Stage Circuit

Problem 3: Write the Boolean expression for this circuit.

A -----+
       |   _____
B -----+--|     \
       |  | AND   )-------+
       +--|_____/         |
                         |   _____
C -----------------------+--|     \
                         |  | OR    )--- Z
D -----------------------+--|_____/
                         |
E -----------------------+
                         |   _____
F -----------------------+--|     |
                         |  | AND  )---+
                         +--|_____/   |
                                           |   _____
G ----------------------------------------+--|     |
                                             | NAND )--- Z_out
H ----------------------------------------+--|_____/

Wait, let me redraw this properly. The circuit has:

AND1: inputs A, B, C → output P
OR1: inputs P, D, E → output Q
AND2: inputs F, G → output R
NAND: inputs Q, R → output Z

Show Solution

Step 1: Identify intermediate expressions

$P = ABC$ (AND1)
$Q = P + D + E = ABC + D + E$ (OR1)
$R = FG$ (AND2)
$Z = \overline{QR} = \overline{Q \cdot R}$ (NAND)

Step 2: Substitute $$Z = \overline{(ABC + D + E) \cdot FG}$$

Or written without the intermediate: $$Z = \overline{ABCFG + DFG + EFG}$$

This can be left in this form or expanded further. The key is identifying the intermediate steps correctly.

Practice Problem — Complete Analysis

Problem 4: For the circuit shown below, determine: a) The Boolean expression b) The truth table (full table) c) The SOP expression

A ----+
      |  _____
B ----+--|     \
      | | AND   )---+
      +--|_____/    |
                     |  _____
C ------------------+-|     \
                    | | OR    )--- Z
D ------------------+-|_____/
                    |
E ------------------+

Show Solution

a) Boolean Expression:

AND gate: inputs A, B, C → $P = ABC$
OR gate: inputs P, D, E → $Z = ABC + D + E$

b) Truth Table (32 rows for 5 inputs, showing key rows):

A	B	C	D	E	$ABC$	$Z = ABC + D + E$
0	0	0	0	0	0	0
0	0	0	0	1	0	1
0	0	0	1	0	0	1
0	0	0	1	1	0	1
…	(D=1 or E=1)				0	1
1	1	1	0	0	1	1
1	1	1	0	1	1	1
1	1	1	1	0	1	1
1	1	1	1	1	1	1

c) SOP Expression: From the truth table, the expression is already in SOP form: $$Z = ABC + D + E$$

This is the same as the Boolean expression we derived — a good verification!

Summary

Analysis Process Checklist

Step	Action
1	Identify all gates and their types
2	Trace all signal paths from inputs to output
3	Write intermediate expressions for each gate output
4	Combine to get final expression
5	Build truth table by evaluating expression

Gate Output Formulas

Gate Type	Output Expression
AND	$P = A \cdot B \cdot C …$
OR	$P = A + B + C …$
NAND	$P = \overline{A \cdot B \cdot C…}$
NOR	$P = \overline{A + B + C…}$
XOR	$P = A \oplus B$
NOT	$P = \overline{A}$

Common Mistakes to Avoid

Forgetting bubbles/inversions in the expression
Skipping intermediate steps when circuits get complex
Not checking all inputs are accounted for
Mixing up AND (·) and OR (+) operations

Key Reminders

Always work left-to-right through the circuit
Use intermediate variables (P, Q, R) to simplify complex circuits
A bubble on an input means use the complemented variable
Verify your expression matches the original circuit topology
Truth tables with $n$ inputs have $2^n$ rows
SOP expression from analysis may need expansion to show all minterms
Double-check gate shapes match the operation (AND = flat inputs, OR = pointed inputs in ANSI)

Custom activity — adapted from PLTW Digital Electronics

A	B	C	D	$AB$	$Z = AB + C + D$
0	0	0	0	0	0
0	0	0	1	0	1
0	0	1	0	0	1
0	0	1	1	0	1
0	1	0	0	0	0
0	1	0	1	0	1
0	1	1	0	0	1
0	1	1	1	0	1
1	0	0	0	0	0
1	0	0	1	0	1
1	0	1	0	0	1
1	0	1	1	0	1
1	1	0	0	1	1
1	1	0	1	1	1
1	1	1	0	1	1
1	1	1	1	1	1

A	B	C	D	$AB$	$Z = AB + C + D$
0	0	0	0	0	0
0	0	0	1	0	1
0	0	1	0	0	1
0	0	1	1	0	1
0	1	0	0	0	0
0	1	0	1	0	1
0	1	1	0	0	1
0	1	1	1	0	1
1	0	0	0	0	0
1	0	0	1	0	1
1	0	1	0	0	1
1	0	1	1	0	1
1	1	0	0	1	1
1	1	0	1	1	1
1	1	1	0	1	1
1	1	1	1	1	1

A	B	C	D	$AB$	$Z = AB + C + D$
0	0	0	0	0	0
0	0	0	1	0	1
0	0	1	0	0	1
0	0	1	1	0	1
0	1	0	0	0	0
0	1	0	1	0	1
0	1	1	0	0	1
0	1	1	1	0	1
1	0	0	0	0	0
1	0	0	1	0	1
1	0	1	0	0	1
1	0	1	1	0	1
1	1	0	0	1	1
1	1	0	1	1	1
1	1	1	0	1	1
1	1	1	1	1	1