Logic Levels & Digital Signals

Logic levels are specific voltage ranges that digital circuits use to represent binary values (1s and 0s).

What Are Logic Levels?

In digital electronics, transistors function as electronic switches. Instead of processing raw analog values, they represent information using two distinct logical states. Rather than expecting a single exact voltage, digital devices use voltage ranges to define these states.

Why Do We Use Voltage Ranges?

If digital circuits expected exactly 5.0V for HIGH and exactly 0.0V for LOW, they would constantly fail. Digital circuits rely on ranges for three reasons:

• Consistency: Ensures different chips in a system agree on logic states.
• Noise Immunity: Prevents small fluctuations in voltage from corrupting the logical value.
• Manufacturing Tolerances: Accounts for physical variations in silicon fabrication and resistance across wires.

Different semiconductor technologies have distinct voltage standards. The two main families are TTL (bipolar transistors) and CMOS (field-effect transistors).

Comparing Logic Standards

A logic family defines four critical threshold voltages. Notice how TTL uses fixed thresholds, while classic 5V CMOS thresholds are ratiometric (defined as 70% and 30% of supply voltage VCC):

• V_OH (Output HIGH): The minimum voltage an output gate guarantees to output for a 1.
• V_OL (Output LOW): The maximum voltage an output gate guarantees to output for a 0.
• V_IH (Input HIGH): The minimum voltage an input gate guarantees to recognize as a 1.
• V_IL (Input LOW): The maximum voltage an input gate guarantees to recognize as a 0.

Threshold & Noise Margin Simulator

Use the simulator below to compare standard TTL thresholds with CMOS thresholds. Drag the voltage slider to see how input receivers interpret the voltage, and notice the undefined transitional zone.

Noise margin is the safety buffer voltage that prevents electromagnetic noise from corrupting digital states.

Calculating Noise Margin

Noise margins are calculated separately for the HIGH and LOW states using the differences between output guarantees and input requirements:

HIGH Noise Margin (NMH):
  NMH = VOH - VIH
  TTL example: 2.4V - 2.0V = 0.4V

LOW Noise Margin (NML):
  NML = VIL - VOL
  TTL example: 0.8V - 0.4V = 0.4V

Why Digital is Noise-Resistant

Imagine a digital wire routing a HIGH state from a TTL gate. The driver guarantees a minimum of 2.4V. As it travels down the line, nearby AC wiring induces 0.3V of negative noise. The receiver sees 2.1V. Since 2.1V is still above the V_IH minimum input threshold of 2.0V, the receiver successfully reads a clear HIGH! The noise has zero impact on the logical state.

Digital signals are represented by pulses that switch rapidly between HIGH and LOW states, forming a square wave.

Transition Times

No signal can change voltage instantaneously; it takes time for charge to build up or drain away. We measure these transitions using rise and fall times:

• Rise Time (t_r): The time it takes for a signal to transition from 10% to 90% of its final amplitude.
• Fall Time (t_f): The time it takes for a signal to transition from 90% to 10% of its final amplitude.

Pulse Parameters

When analyzing a repeating square wave pulse, we look at several standard dimensions:

Digital waveforms can be analyzed mathematically using formulas for Period, Frequency, and Duty Cycle.

Governing Formulas

Worked Examples

Example 1 (Period): A clock signal has a frequency of 1 kHz (1000 Hz). What is its period?

Example 2 (Frequency): A pulse train has a period of 20 ms. What is its frequency?

Example 3 (Duty Cycle): A clock has a period T of 100 µs and stays HIGH (PW) for 30 µs. What is its duty cycle?

Practice Problems